DEVELOPMENT OF A QUEUING SYSTEM ON FPGA FOR PROCESSING ETHERNET PACKETS

A scheme for buffering Ethernet packets hardware implementation of their processingbased on FPGA has been developed. The is designed at the RTL level in System Veriloglanguage Quartus II 13.1 development environment. Verification and modeling werecarried out ModelSim Altera An CycloneIV family, located theA processing based onFPGA Verilog languagein were carriedout theDE2-115 debugging board, was chosen as target platform. Particular attention paid to datareception transmission modules, well a queue (FIFO)with possibility changing its contents by module. parameterized,it allows you change depth expense one parameter without makingchanges other parts scheme. feature ability add any hardwaremodule that monitors, processes or encrypts network traffic. MII interface used transmittingand receiving packets, which using available physical layer chips receivingand transmitting packets. device easily input output interface,which increases versatility. system does not use proprietary IP cores, makes it asportable possible FPGAs from various manufacturers. main thelow delay between sending packet, determined only parameters processingmodule. results work can be applied during design devices transmitdata with preprocessing. For example, equipment (switches, routers), monitoring anddata collection systems.